In a device for diving an electrical load by supplying a direct current to the electrical load through a driving transistor (i.e., output driver), switching noise occurs due to a change in the current flowing through the electrical load. As one simple approach to reduce such switching noise, a resistance value of a resistor connected to the gate of the driving transistor is increased so that a gas signal waveform can be slowed due to a RC time constant of the resistance value and a gate capacitance. However, when a gate signal level exceeds a threshold voltage Vt of a FET, an energizing current increases sharply. Therefore, this approach may be insufficient to reduce harmonic noise.
As another approach to reduce such switching noise, a gate signal is caused to have a trapezoidal waveform. This approach can reduce a low-order harmonic wave but cannot reduce a high-order harmonic wave caused by corner portions of the trapezoidal waveform. US 2006/0267665 corresponding to JP-A-2007-13916 discloses a structure for causing a gate signal to have a near-sinusoidal waveform, thereby reducing such switching noise.
However, since the structure disclosed in US 2006/0267665 needs many current sources and comparators, the structure is increased in size and complexity.
JP-A-H9-8639 discloses a structure for preventing a shoot-through current from flowing between a power supply voltage and a ground in a signal output section of a CMOS. In the structure, multiple FETs are connected on each of a PMOS side and a NMOS side to remove a timing lag when each FET is switched to an OFF state and to create a timing lag when each FET is switched to an ON state. This structure may prevent the shoot-through current. However, since an electric current greatly changes when the gate voltage of each FET changes near a threshold voltage Vt of the FET, a noise reduction effect may be small. Further, the structure disclosed in JP-A-H9-8639 is increased in size and complexity.
JP-A-H11-136108 discloses a structure for reducing a switching noise. In the structure, multiple P-channel MOSFETs for signal output are connected in parallel, and the gate of each FET is individually provided with a level shift circuit. Further, ON-timings of the FETs are changed by using multiple delay circuits so as to reduce the switching noise. However, the structure disclosed in JP-A-H11-136108 is increased in size and complexity compared to the structure disclosed in JP-A-H9-8639.